1. Field of the Invention
This invention relates to improvements in semiconductor integrated circuits and semiconductor fabrication processes, and more particularly to improvements in EEPROM devices, and methods for making the same. The invention relates still more particularly to improvements in the layout and construction of the floating gate element of an EEPROM cell and to EEPROM devices using it. The invention relates still more particularly to improvements in EEPROM devices that have increased floating gate isolation and methods for making same, and to improvements in isolation techniques for isolating a floating gate structure of an EEPROM device.
2. Relevant Background
As advances are made in technologies related to electrically erasable read only memory (EEPROM) devices, EEPROM devices are being introduced into many semiconductor processes, such as CMOS, BiCMOS, linear BiCMOS process, such as LINBICMOS.TM., and other such advanced semiconductor processes. When EEPROM cells are produced for any semiconductor process, factors contributing to improving the ability to manufacture such EEPROM devices, and the potential impact of such factors on reliability of the final devices are of key concern.
Many EEPROM designs rely upon an associated tunnel diode to control the placement and removal of a charge onto and from a floating gate of the device. The tunnel diode typically is constructed with a doped tunnel diode region contained in the semiconductor substrate. Typically, a portion of the floating gate overlies the tunnel region, and is separated from the tunnel region by a thin oxide layer sometimes called the "tunnel oxide" through which charge may be passed to or from the floating gate. The quantity of charge on the floating gate controls the threshold voltage of an associated MOS transistor over the channel of which a portion of the floating gate is also located. The floating gate is generally separated from the channel of the MOS transistor by a thin gate dielectric or oxide. A control gate is also provided over and capacitively coupled to the floating gate. When the state of the EEPROM cell is read, a voltage is applied to the control gate, which is capacitively coupled to the floating gate. Depending upon the quantity of charge on the floating gate, the influence of the control gate voltage will either enable a current flow in the channel of the MOS transistor, or not, allowing the memory state of the cell to be determined.
Among the many considerations that affect design and construction of the tunnel diode region, the thickness and quality of the tunnel oxide are of basic importance. In previous EEPROM devices, the tunnel oxide generally has a thickness of about 100 .ANG., and the quality of tunnel oxide impacts the reliability and performance of the final EEPROM cell.
In the past, in the formation of a tunnel diode in association with the MOS transistor, a first portion of a gate oxidation was performed to provide an initial oxide thickness over the tunnel diode region as well as its peripheral areas. Thicker field oxide may also have been concurrently formed over more highly doped regions of the substrate at which field adjust implants may have been made. The oxide directly over the tunnel region was then stripped to expose the substrate, and a dopant of appropriate type and conductivity to provide the desired tunnel region was introduced or implanted into the substrate.
The exposed substrate area was then again oxidized to produce the proper tunnel oxide thickness, about 100 .ANG.. The surrounding oxide was also concurrently thickened, for example, to a final thickness of about 200 .ANG. to 500 .ANG..
After the tunnel region and oxidation had been completed a polycrystalline silicon (polysilicon) floating gate was deposited patterned, and etched. It can be seen that the underlying oxide layer provided a relatively high quality encapsulation of at least the bottom and sidewall portions of the floating gate structure. During the subsequent construction of the control gate, a high quality dielectric, usually a nitride or other dielectric is formed between the floating and control gates to provide the capacitor dielectric. During subsequent processing, however, the portions of the capacitor dielectric that does not lie between the floating and control gates is generally stripped away, at least in part, to allow implantation of the source and drain elements of the MOS transistor, and to enable other required device structures.
In order to enable the charge to be maintained on the floating gate for extensive periods of time, on the order of ten years or longer, for example, the floating gate structure needs to be completely isolated. The usual isolation techniques employed in the past include the formation of one or more isolation layers on the top side of the floating gate.
In the past, one favored technique for isolating the floating gate involves forming tetraethylorthosilicate (TEOS) sidewalls on the floating gate, and subsequently encapsulating the topside of the floating gate with an additional layer of TEOS, since TEOS is usually used in the fabrication of other components associated with the EEPROM, and its deposition can be easily accomplished. However, the quality of TEOS (i.e., the electron barrier height of TEOS) is not as high as might be desired. In most CMOS processes, TEOS is used to form sidewall spacers on all CMOS gates. It should be noted that even if the topside were to be adequately isolated with a material other than TEOS, charge loss from the sidewalls can still pose a serious problem. Also, the portion of the polysilicon floating gate that overlies the transistor is generally not covered, in order to realize tighter design rules. As a consequence, electrons residing on the floating gate are enabled to tunnel off of the gate faster than might be desired, or even tolerable. The result, of course, is a reduction in the memory lifetime of the EEPROM cell.